The present invention relates to the field of electronic memories, and more specifically to fast dynamic random access memories (DRAMs).
DRAMs are widely used. Indeed, they have the major advantage of having a large storage capacity. However, they have the disadvantage of being slow in terms of access time. Thus, it is desired to minimize this access time or, which amounts to the same thing, to use the memory so as to mask this access time.
In French patent application entitled xe2x80x9cDRAM à structure rapidexe2x80x9d, filed on Mar. 26, 1998, under number 98/04008, the Applicant has endeavored finding a solution to this problem and discloses a DRAM associated with two cache registers located between the DRAM memory plane and a user system.
In another French patent application, entitled xe2x80x9cProcxc3xa9dxc3xa9 de commande de mxc3xa9moire DRAM rapide et contrxc3x4leur adaptxc3xa9xe2x80x9d, filed on Nov. 11, 1999, under number 99/14610, the Applicant describes a method and a controller to control the preceding DRAM. FIG. 1 shows a DRAM of this type.
In FIG. 1, a DRAM 1 includes a memory plane 2, a row decoder 3 controlled by control signals (RAS: Row Address Strobe, RAD: Row ADdress, RWB: Row Write Back) and a column decoder 4 controlled by signals (CAS: Column Address Strobe, CAD: Column ADdress, R/W: Read/Write). Memory 1 also includes an input DIN and an output DOUT enabling reading and writing of data.
Memory 1 also includes two cache registers A and B located between the memory plane and the column decoder. The presence of cache registers A and B enables, when one of the cache registers is in communication with the memory plane, writing or reading data in the other register. This results in a masking of the time of access to the memory plane. If the bursts relating to a same page are long enough, a continuous output data flow can be obtained. Also, if the bursts (xe2x80x9cburstxe2x80x9d designates a series of requests relating to the same page) are long enough, a totally masked memory refreshment can be performed.
A disadvantage of the structure of FIG. 1 is that, if the average burst duration is short, the output flow is not continuous.
Another disadvantage of the structure of FIG. 1 is that two accesses to the memory plane are necessary during a write operation. Indeed, it is first required to load the page to be modified in a cache register from the memory plane. Then, after the page contained in the cache register has been modified, the modified page must be rewritten into the memory plane, which requires a new access to the memory plane. In this case, for the output flow to remain uninterrupted, the bursts must have a duration at least equal to that of two cycles of access to the memory plane and, if a refreshment order is further input, a duration of at least three cycles of access to the memory plane.
The disclosed embodiments of the present invention overcome these disadvantages.
The disclosed embodiments of the present invention provide a DRAM circuit having an improved access time.
Another aspect of the present invention is to provide a DRAM circuit and a method for controlling the circuit enabling obtaining a significant time gain for all bursts, be they long (for example, an entire word page) or short.
A further aspect of the present invention is to provide a DRAM circuit and a method for controlling the circuit enabling obtaining a continuous output data flow, as in the case of a SRAM.
Yet another aspect of the embodiments of the present invention is to provide a DRAM circuit and a method for controlling the circuit enabling writing into a DRAM with a single access to the memory plane.
A further aspect of the present invention is to provide a DRAM circuit and a method for controlling the circuit that decreases the minimum burst duration enabling uninterrupted data supply by a DRAM.
To achieve the foregoing advantages and features as well as others, the embodiments of the present invention provide a dynamic random access memory (DRAM) circuit including a memory plane formed of an array of memory cells organized in rows and columns, a row decoder and a column decoder, each row of the memory plane corresponding to a word page. The memory circuit includes:
at least two cache registers coupled with the memory plane enabling reading words from a memory page and/or writing new words into a memory page, and
several locating circuits or means, each of the locating means being coupled with one of the cache registers adapted to ensure a memory writing, and indicating the position, in the page, of the new words to be written into the memory.
According to an embodiment of the present invention, each of the cache registers is adapted to storing a complete word page.
According to another embodiment of the present invention, the cache registers are located between the memory plane and the column decoder.
According to a further embodiment of the present invention, each of the locating means is a register including as many bits as there are words in a page.
According to another embodiment of the present invention, the number of cache registers is equal to four, two cache registers being used for the reading, the two other cache registers being used for the writing, and the number of locating means is equal to two, each of the locating means being coupled with one of the two cache registers used for the writing.
According to yet another embodiment of the present invention, the number of cache registers is equal to three, said cache registers being usable indifferently for the reading or the writing, and the number of locating means is equal to three, each of the locating means being coupled with one of the cache registers.
According to a further embodiment of the present invention, the number of cache registers is equal to two, said cache registers being usable indifferently for the reading or the writing, and the number of locating means is equal to two, each of the locating means being coupled with one of the cache registers.
The embodiments of the present invention also provide a method for controlling a dynamic random access memory (DRAM) circuit including a memory plane formed of an array of memory cells organized in rows and columns, each row corresponding to a word page, a row decoder, a column decoder, and at least two cache registers coupled with the memory plane for reading and/or writing. The method includes, in write mode, the steps of:
(a) receiving a request for writing a new word into the memory, including a row address corresponding to the page of the new word, a column address corresponding to the location in the page of the new word, and said new word, the request being part of a series of requests,
(b) storing the new word to be written in one of the cache registers adapted to ensuring a writing,
(c) finding the location of the new word by means of a locating means coupled to said cache register,
(d) repeating steps (b) and (c) as long as the next received request is a write request concerning the same page, and
(e) when the next received request no longer is a write request concerning the same page, transferring into the memory plane said new words stored in said cache register by means of said locating means, the transfer occurring as soon as possible if said next received request is a write request concerning a different page, and the transfer being postponed if said next request is a read request.
According to an embodiment of the present invention, in the case of a reading concerning a page including new words waiting to be written stored in a first cache register, the method includes the steps of:
loading, from the memory plane, the considered page into a second cache register adapted to ensuring a reading,
providing for a reading one or several desired words, said word(s) coming from said first cache register if these are new words waiting to be written, and said word(s) coming from said second cache register in the opposite case.
According to an embodiment of the present invention, in the case of a reading concerning a page including new words waiting to be written into a first cache register, the method includes the step of:
loading a second cache register adapted to ensuring a reading with the words of the considered page, these words coming from said first cache register if they are new words waiting to be written and coming from the memory plane in the opposite case.
The foregoing features and advantages of the embodiments of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.